There are a number of prior art techniques to simulate large circuits with repetitive sub-circuits (e.g., a memory array). To simulate such circuits, the state of every circuit element must be represented. Some of these techniques include hierarchical circuit simulation, symbolic simulation, and symbolic model checking.
In hierarchical circuit simulation, repetitive sub-circuits states are stored in a hierarchical form with each sub-circuit being evaluated n times if there are n instances of the subcircuits. However, there is still an explicit record for the state of every circuit node.
In symbolic simulation, symbolic encoding is used to describe the state of a circuit over many operating conditions. After using symbolic encoding, symbolic evaluation is used so that each circuit element computes the behavior of each element for all of the encoded state cases. Each evaluation only computes the behavior of one instance of a circuit element. There is an explicit record of the state of every circuit node.
In a symbolic model checking, the set of all possible system states is encoded symbolically. Symbolic evaluation is used to determine the effect of each possible state transition for each of these possible states. Even so, there is an explicit representation of every circuit state variable.
There are other prior art techniques to handle larger circuits with repetitive sub-circuits for other purposes. For example, Design Rule Checking (DRS) is one of these techniques. In performing DRC on a large circuit, hierarchical information is exploited to take advantage of the repetitive circuit structures to speed up the checking. However, DRC does not require the recording of states of circuit elements dynamically.